哪些CPU(如果有)具有8位地址空間?


20

即使是具有4位字長的Intel 4004,也具有12位地址空間。我想知道是否有任何商用CPU具有用於程序,數據或兩者的8位或類似地址空間。

我對具有較小程序地址空間的CPU及其在此類限制下能夠解決的問題類型特別好奇。我人數略少,但仍然對具有較小地址空間的CPU感興趣。

10

Not strictly an answer, but some early computers had very limited addressing. The Harwell Dekatron computer, which operates entirely in decimal, has an address space of 100 words, of which 90 are RAM and the other 10 are devices. Programs for it are usually run directly from a paper tape device (where the tape, rather than the PC register, is advanced after reading each program word), but subroutines can also be loaded into RAM and run from there.

Among architectures with multiple address spaces, the Z80 has an 8-bit I/O address space which is separate from the 16-bit one used for programs and data. But this is probably not what the OP is asking for.


12

The first that comes to mind is Cypress' M8C core used in the PSOC-1 series. While it has a 16 bit program address space (and thus 16 bit jump instructions), its data as well as the register space are each strictly 8 bit.

Implementations do use up to two sets of 256 registers and may offer several sets of 256 Byte banks. From the manual:

The M8C is an 8-bit CPU with an 8-bit memory address bus. The memory address bus allows the M8C to access up to 256 bytes of SRAM,[...]

To take full advantage of the paged memory architecture of the PSoC device, several registers must be used and two CPU_F register bits must be managed.

Interrupt routines are always located in page 0, Stack by default. Data may reside in any page. Access is handeled by a set of registers:

  • CUR_PP holds the current active (default) page
  • STK_PP holds the stack page
  • IDX_PP holds the page used for all indirect address (yes, even indirect pointers are only 8 bit)
  • MVR_PP and MVW_PP hold the pages the MVI instruction operates on (MVI can do indexed memory access with pointer increment)

Two bits in the CPU flag register (*1) define the page mode:

  • No Paging (also during interrupt)
  • Indexed modes use the stack page (including stack instructions)
  • Direct mode use CUR_PP, indexed use IDX_PP
  • Direct mode use CUR_PP, indexed use STK_PP

I seriously love this CPU. It's as close as it can get to a strict 8 bit CPU while being able to solve real world tasks. It's my personal favourite for a CPU as simple as possible without getting lost in academic games (*2).

All data is always only 8 bit. All instructions carry either

  • no parameter, or
  • one parameter one holding an 8 bit address or 8 bit constant, or
  • two parameters holding either two 8 bit addresses or an address and an 8 bit constant.

The only exceptions are LONG JUMP and LONG CALL holding a 16 bit program address (yes, there's a short CALL, using only an 8 bit offset :). Programm memory access for data purpose features the only complex (one byte) instruction, with an address to be prepared in registers. Everything else is quite regular and straight on.

Despite being 8 bit and quite simple it features some of the elegance of a /360.


*1 - Which is not special but part of the register file like any other, thus accessible with all register instructions.

*2 - Not to mention the incredible versatile I/O units. In some sense configurable processors of their own!


22

The KENBAK-1 has 256 bytes of memory. I'm not certain whether it had an 8-bit PC.

https://en.wikipedia.org/wiki/Kenbak-1


6

The Intel 8048 which was used in the Magnavox Odyssey2 had an 8-bit external address bus.


29

PIC: 7 bit address space

The Microchip PIC family of CPUs specifically the 10, 12 and 16 series have 7 bits of address space. While 7 bits is not exactly 8 bits this shows that there are commercial CPUs still on sale and still widely used that have less than 8 bit address space (they are used for example for power management on some Macs and are the most common CPU for smart cards).

However it does not meet some of your requirements because your requirements have some assumptions that does not necessarily hold for some CPU architectures.

For example, you asked about possessing an 8-bit PC. This makes several assumptions that are partly true and partly false for the PIC:

  1. The PIC is a Harvard architecture. The framing of the question has a hidden assumption of a Von-Neumann architecture where program instructions and data have the same address space. For the PIC it has a 7 bit data and 11 bit program address space. So it does not have an 8 bit PC.

  2. However, the PIC cannot process more than 8 bits of data. Therefore the PC is mapped to two separate registers. Reading from and writing to the PC is done 8 bits at a time even though the full address space is 11 bits. So processing the PC, as in accessing it, is done in 8 bits.

Even weirder CPUs

There are other architectures that fall even further from you assumptions. For example stack machines are CPUs that have 0 bit data address space. However, like the PIC, they have different program address space.

The main advantage is that you don't have to encode addresses at all in your instruction set allowing you to have very small instructions. Home-made stack machines such as Lisp or Forth machines can go down to using as few as 3 bits to encode instructions.

If you wonder how we can do computing without any addressing I suggest you look at the programming language Forth (like Lisp, the language is so simple that people have designed hardware implementations of them so it is not merely a programming language but also the instruction set for some CPUs)


4

Not quite there, but close, is the VT52 text terminal with a CPU that has a 10-bit code address space. The data address space is 11 bits.

As answered by others, low end microcontrollers may well have 8-bit code and/or address spaces.


3

The RCA 1802 CPU had only 8 address lines, which were time multiplexed to specify a 16 bit address.

It was used in "telly tennis" type game machines in the mid 1970's and early home computers like the COSMAC ELF as well as the Hubble space telescope.

Just recently my retired neighbour was regaling me with stories of when he was developing a system with two of these CPUs; One to run code in 2Kb of RAM and the other to bit-bang RS-232.


1

The DEC PDP-8, a 12-bit machine with 4k words of memory, had 8-bit direct addressing (7-bit offset and a 1-bit Page Zero selector). However, an Indirect bit in the order code caused the contents of the directly addressed location to be used as a 12-bit address of the real operand. Later models of the PDP-8 family could have up to 7 more "Fields" of memory, each with 4k words, which could be addressed only indirectly, having first set the required Data Field (0-7) by means of a pseudo Input/Output Transfer (IOT) instruction.